1. Field of the Invention
The present invention relates to a technique for design verification performed in developing an electronic circuit such as a printed circuit board. The present invention relates particularly to a design verification apparatus, a design verification program, a design verification method, and a CAD (computer aided design) apparatus that, by preparing data for design verification, enable the processing time for the design verification to be reduced.
2. Description of the Related Art
FIG. 19 is a chart illustrating the development flow for a printed circuit board. The development work for an electronic circuit such as a printed circuit board is performed in accordance with sequential steps, e.g., specification design (P10), circuit design (P12), mounting design (P14), analysis (P15), and trial board production (P16).
The specification design (P10) is a process of determining a specification including a system requirement that specifies functions to be realized, a component configuration, an operating frequency, a bus configuration, and the like and production conditions that specify arrangement restriction, the number of layers, and the like. A specification is a document in which specifications determined in the specification design (P10) are described.
Floor planning/analyses (P11 and P13) are processes in which limiting conditions for the circuit design (P12) and the mounting design (P14) are studied and created. Depending on the results of the floor planning/analyses (P11 and P13), the specifications themselves are modified. The limiting conditions (design-restriction DB) are restrictions, such as arrangement positions for components, the wiring lengths of net lines, wiring spacing, and the number of bypass capacitors, on the circuit design (P12) and the mounting design (P14); the limiting conditions are created in the specification design (P10) and the floor planning/analyses (P11 and P13) so that no problem is posed when printed circuit boards are produced.
In the Floor planning/analyses (P11 and P13), an actual layer configuration, a component arrangement, and a wiring pattern are created, as limiting conditions on designing, based on the specifications determined in the specification design (P10). In addition, by utilizing the created limiting conditions, an analysis, e.g., of a power-source noise is performed. Based on the analysis, it is verified that no problem is posed in producing printed circuit boards; if any problem exists, the limiting conditions are reviewed and modified. The circuit design (P12) and the mounting design (P14) are performed in accordance with the limiting conditions that, as described above, have been modified, while being verified, so as to prevent any problem from occurring. As a result, at the early stage of the development, the occurrence of problems can be prevented that, to date, have been found later in the production of printed circuit boards.
The circuit design (P12) is a design process of connecting by means of net lines a plurality of components such as ICs, resistors, and capacitors, power sources, and the ground with one another so that the functions of a system are realized. A net list is data for circuits that are created in the circuit design (P12). The net list includes constituent elements of a printed circuit board, such as components, power sources, and the ground, and information on connection between the constituent elements.
The mounting design (P14) is a design process in which actual arrangement and wiring on the substrate are performed by utilizing the data created in the circuit design (P12). Layout data is created in the mounting design (P14). In addition to the information in the net list, the layout data includes the actual shapes of components and nets and information about the positions of the constituent elements on a printed circuit board.
The analysis (P15) is a process in which whether or not any production problem is posed is analyzed by utilizing the layout data. Basically, the analysis (P15) is the same as what are performed in the floor planning/analyses (P11 and P13); however, the accuracy of the analysis (P15) is higher than those of the floor planning/analyses (P11 and P13), owing to the layout data. CAM (Computer Aided Manufacturing) data is conveyed to the production line of a factory and with which an actual printed circuit board is produced; the CAM data is converted from the layout data.
The trial board production (P16) is a process in which a prototype of the printed circuit board is produced. An actual-equipment test on the prototyped printed circuit board is performed; when no problem is posed, actual production (mass production) of the printed circuit board is started.
FIG. 20 is a diagram illustrating a configuration example of a CAD apparatus. In the circuit design (p12) in the development flow represented in FIG. 19, the designer of a printed circuit board performs circuit design, by utilizing an application for the circuit design. A CAD apparatus 110 includes a component library 111, a circuit-design processing unit 112, a circuit database 113, and a DRC execution unit 114.
In response to the designer's manipulation of an input/output device 120, the circuit-design processing unit 112 performs circuit design processing. By manipulating the input/output device 120, the designer selects components to be used from the component library 111 and inputs the components to a circuit diagram. The component library 111 is a library of components to be utilized in a circuit. The circuit database 113 is a database for storing the circuit data for the circuit diagram that is created by the designer. The created (or in process of creation) circuit diagram is outputted to and displayed on the input/output device 120.
The DRC execution unit 114 is incorporated in a design verification unit 115 of the CAD apparatus 110 and executes a DRC (Design Rule Check) on the designed circuit diagram (the circuit data stored in the circuit database 113). Verification work is required in which, after the completion of the circuit design, the authenticity of the circuit (whether the circuit complies with the design criteria) is verified. For the verification, a scheme is utilized that is referred to as a DRC and in which the authenticity of a circuit is automatically checked based on a design rule.
The verification items to be checked are roughly divided into a drawing check for pointing out errors in the notation of a circuit diagram and a logic check for pointing out errors in the logical configuration of a circuit. In the drawing check, whether or not any error in the notation of a circuit diagram exists is checked, i.e., a check on cross wire connection, a check on component arrangement outside the drawing frame, a check on overlap of a character and a component, and the like are checked. In the logic check, whether or not any error in the logical configuration of a circuit exists is checked, i.e., a check on whether or not any unconnected power-source pin exists, a check on whether or not a case exists in which no input pin or output pin exists in a net, a check on dot logic (a case where one input pin is driven by way of a plurality of output pins), and the like are checked.
After executing the DRC, the DRC execution unit 114 reports to the designer the positions where the foregoing rule is not complied with. When any error is pointed out, the designer modifies the circuit diagram, in accordance with the report on the result of the DRC execution.
In addition, in the case where, through the logic check, the authenticity of the logical configuration of a circuit is verified, it may be considered that a component whose input and output logically take the same value, e.g., whose input-pin signal and output-pin signal are equal, does not exist. Components that are logically transparent, as described above, are referred to as logically transparent components.
The logically transparent components include, e.g., a dumping resistor, and a coupling capacitor. A resistor that is not connected to either of the power source and the ground, but connected between the nets of ordinary signals is referred to as a dumping resistor. A capacitor is a component that accumulates electricity therein, and only from that point of view, it may be utilized simply in place of a battery; however, in an electronic circuit, capacitors are scarcely utilized for that purpose. A capacitor is conductive for AC current and nonconductive for DC current, in nature; therefore, it is utilized in the case where the electric potentials at both sides differ from each other and it is required to transfer only AC current. A capacitor that is utilized for that application is referred to as a coupling capacitor.
To date, a designer has manually inputted these logical types (a dumping resistor, a coupling capacitor, and the like) of components to the CAD apparatus 110.
In addition, a component logical type signifies the logical type into which the component is classified in accordance with the in-circuit properties of the component. Additionally, a component type signifies the type of the component itself. For example, components whose component type is “resistor” are logically classified in line with roles in a circuit, e.g., into a “dumping resistor”, a “pull-up resistor”, and a “pull-down resistor” that are the component logical types.
FIG. 21 is a diagram illustrating a configuration example of circuit data. Circuit data stored in the circuit database 113 consists of four data tables, i.e., a circuit diagram table 130, a component table 131, a component pin table 132, and a net table 133. The respective data tables are linked with one another in such a way as to correspond to the circuit configuration. The mark “*” in FIG. 21 stands for one or more pieces.
The circuit diagram table 130 is a data table for managing information on the whole circuit diagram. The circuit diagram table 130 is created for each circuit diagram. The circuit diagram table 130 is linked with a plurality of the component tables 131 and a plurality of the net tables 133.
The component pin table 131 is a data table for managing information on components included in a circuit diagram. When the designer adds a component to a circuit diagram, a single component table 131 is added. The component table 131 is linked with a plurality of the component pin tables 132.
The component table 132 is a table for managing information on a plurality of component pins of each component. The component pin table 132 is linked with the parent component table 131 and the connected net table 133. The case never takes place in which a single component belongs to a plurality of parents. Additionally, the number of component pins that each component has is defined in the component library 111 and the designer cannot alter in the circuit design. When a component is added to a circuit diagram, the component pin tables 132 are automatically created; the number of the component pin tables 132 is the same as that of pins of the component.
The net table 133 is a data table for managing information on nets included in a circuit diagram. When the designer adds a net to a circuit diagram, the single net table 133 is added. The net table 133 is linked with the connected component pin tables 132.
FIG. 22 is a diagram illustrating an example of a circuit diagram. In the circuit diagram (sample) in FIG. 22, a component A has a component pin PA; a component B has a component pin PB; a component R has component pins PR1 and PR2; a component C has component pins PC1 and PC2. A net N1 connects the component pin PA and the component pin PR1; a net N2 connects the component pin PR2 and the component pin PC1; a net N3 connects the component pin PC2 and the component pin PB. In FIG. 22, it is assumed that the components R and C are a resistor and a capacitor, respectively, to be considered as a logically transparent component.
FIG. 23 is a diagram illustrating an example of the structure of a database for a circuit diagram. FIG. 23 is a database structure that represents the circuit diagram (sample) illustrated in FIG. 22. In the case where, with regard to logical connection of the circuit diagram illustrated in FIG. 22, the link from the component pin PA to the component pin PB is obtained, it is required to access the database in accordance with the following procedure:                Procedure 1: the link from the component pin PA of the component A to the net N1 is obtained;        Procedure 2: the link from the net N1 to the component pin PR1 is obtained;        Procedure 3: the link from the component pin PR1 to the component R is obtained;        Procedure 4: the link from the component R to the component pin PR2 is obtained, because the component R is a logically transparent component (resistor);        Procedure 5: the link from the component pin PR2 to the Net N2 is obtained;        Procedure 6: the link from the Net N2 to the component pin PC1 is obtained;        Procedure 7: the link from the component pin PC1 to the component C is obtained;        Procedure 8: the link from the component C to the component pin PC2 is obtained, because the component C is a logically transparent component (capacitor);        Procedure 9: the link from the component pin PC2 to the net N3 is obtained; and        Procedure 10: the link from the net N3 to the component pin PB is obtained.        
FIG. 24 is a flowchart illustrating logic check processing carried out by the DRC execution unit. The logic check processing carried out by the DRC execution unit 114 differs depending on the contents to be checked. Here, as an example, processing will be explained in which whether or not any input pin exists in component pins connected to one net is checked. In this processing, when no input pin exists in component pins connected to one net, “error” is outputted. This kind of connection may suggest that the circuit is not normal. It is assumed that, before the start of the processing, respective processed flags for the tables are set to the initial setting values “OFF”.
In the first place, all nets are obtained from the circuit diagram (Step S100). In other words, all the net tables 133 that are linked with the circuit diagram table 130 are obtained. Hereinafter, it is assumed that, similarly, the processing is carried out by utilizing information on the tables.
When no unprocessed (processed flag=OFF) net exists in the nets obtained in Step S100 (Step S101), the processing is ended.
When any unprocessed (processed flag=OFF) net exists in the nets obtained in Step S100 (Step S101), one unprocessed net is selected (Step S102), component-pin searching processing described later is carried out (Step S103), and a component pin list is created. The component pin list is a list for the component pins that are considered to be logically connected to the same net when the search is executed, while logically transparent components are logically penetrated.
When no input pin exists in the component pin list created through the component-pin searching processing (Step S104), the error information on the net selected in Step S102 is outputted (Step S105). The processing in Step S101 is resumed. The error information outputted in Step S105 is, for example, an error message such as “the net (name) is not connected to any input pin”.
FIG. 25 is a flowchart illustrating the component-pin searching processing. With a net considered as an input, the component-pin searching processing is carries out.
In the first place, all component pins connected to the obtained (or selected) net are obtained (Step S10). In other words, all the component pin tables 132 that are linked with the net table 133 are obtained. In addition, the processed flag of the obtained (or selected) net is set to ON (Step S111).
When no unprocessed (processed flag=OFF) component pin exists in the component pins obtained in Step S110 (Step S112), the processing is ended.
When any unprocessed (processed flag=OFF) component pin exists in the component pins obtained in Step S110 (Step S112), one unprocessed component pin is selected (Step S113) and the processed flag of the component pin selected in Step S113 is set to ON (Step S114).
When the parent component of the component pin selected in Step S113 is a logically transparent component (Step S115), the component pin, of the parent component, opposite to the component pin selected in Step S113 is obtained (Step S116). Next, the processed flag of the component pin obtained in Step S116 is set to ON (Step S117). A net connected to the component pin obtained in Step S116 is obtained (Step S118), and the component-pin searching processing is recursively carried out (Step S119). The processing in Step S112 is resumed. In addition, whether or not a component is a logically transparent component is determined based on the component logical type and the like.
When the parent component of the component pin selected in Step S113 is not a logically transparent component (Step S115), the component pin selected in Step S113 is stored in the component pin list (Step S120). The processing in Step S112 is resumed.
The literatures in which a prior art related to circuit verification is described are exemplified by, for example, Patent Document 1. Patent Document 1 discloses a technique for reducing the processing time for analogue simulation of delayed computation in the mounting design of a large-scale semiconductor integrated circuit (LSI).                (Patent Document 1: Japanese Patent Laid-Open No. 2001-101245)        
To date, in the case where, in the application of circuit design, the DRC is carried out, circuit data stored in the circuit database 113 has been utilized. However, it has been a problem that, when the circuit diagram becomes large-scale, the number of components and nets increases, whereby it takes a long processing time to perform the DRC. Generally, in the DRC, several dozen to several hundreds, or more, kinds of checks are performed; therefore, if, each time the check is carried out, the circuit configuration is referred to in accordance with the procedure explained utilizing FIGS. 22 and 23 as an example, massive processing time, in proportion to the circuit scale, is consumed.
Moreover, it has been required that the component logical types that, in the DRC, is necessary for detecting logically transparent components are manually inputted by a designer; therefore, in the case where the number of components is large, the DRC has been a cause of increase in work amount of the designer. If the logical types of components related to the logical transparency are not correctly set, erroneous results are outputted through the DRC. Accordingly, it has been a problem that errors inherent in the design and pseudo errors caused by mistaken setting or insufficient setting of component logical types are intermingled, whereby it takes long time to sort the causes and to address the problem.
In addition, the technique disclosed in Patent Document 1 does not have an object of reducing the processing time for design criteria verification (DRC) in circuit design of a printed circuit board (PCB). In general, in the PCB circuit design, the analogue simulation of the delayed computation is not performed. That is because information which is to be included in the layout data, such as the positional information on components and conducting wires, necessary for the delayed computation of conducting wires is not provided. In summary, the technique disclosed in Patent Document 1 cannot be applied to the circuit design data.
Node information, which is supposed to be unnecessary for the analogue simulation of delayed computation, is required for the design criteria verification (DRC) in the circuit design of a printed circuit board (PCB); therefore, because, provided the technique disclosed in Patent Document 1 is utilized, even necessary data may be reduced, the application of the technique is not practical. Because the DRC has nothing to do with electric current paths, data cannot be reduced by the current-path-search parasitic capacitance aggregation means and the specific wiring parasitic resistance extraction means disclosed in Patent Document 1.